Design and Implementation of Handwritten Digit Recognition Accelerator Based on Systolic Array

Abstract Due to the rapid development in artificial intelligence, classic Von Neumann architecture is no longer able meet demands of high-computing, high-storage, and high-bandwidth intelligence applications. To address this issue, paper proposes a handwritten digit recognition accelerator based on systolic array. First, 5 convolutional layer network built. Besides, The FPGA-based convolution employs im2col technology convert calculations into matrix multiplications uses array efficiently perform these multiplications. Furthermore, four processes are pipelined improve throughput. Finally, system implemented PYNQ-Z2. Compared with software implementation Arm, speedup 598x, delay 1.24 s, power consumption 2.51 w.